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K6X4016T3F Family
Document Title
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No
0.0 0.1
History
Initial draft Revised - Added Commercial product - Deleted 44-TSOP2-400R Package Type. - Added 55ns product(@ 3.0V~3.6V) Finalized Revised - Changed ICC(Operating power supply current) from 4mA to 2mA - Changed ICC1(Average operating current) from 4mA to 3mA - Changed ICC2(Average operating current) from 40mA to 25mA - Changed ISB1(Standby Current(CMOS), Commercial) from 15A to 10A - Changed ISB1(Standby Current(CMOS), Industrial) from 20A to 10A - Changed ISB1(Standby Current(CMOS), Automotive) from 30A to 20A - Changed IDR(Data retention current, Commercial) from 15A to 10A - Changed IDR(Data retention current, Industrial) from 20A to 10A - Changed IDR(Data retention current, Automotive) from 30A to 20A
Draft Date
July 29, 2002 December 2, 2002
Remark
Preliminary Preliminary
1.0
August 8, 2003
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 1.0 August 2003
K6X4016T3F Family
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
* Process Technology: Full CMOS * Organization: 256K x16 * Power Supply Voltage: 2.7~3.6V * Low Data Retention Voltage: 2V(Min) * Three State Outputs * Package Type: 44-TSOP2-400F
CMOS SRAM
GENERAL DESCRIPTION
The K6X4016T3F families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature range and have 44-TSOP2 package type for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family K6X4016T3F-B K6X4016T3F-F K6X4016T3F-Q Operating Temperature Vcc Range Commercial(0~70C) Industrial(-40~85C) Automotive(-40~125C) 2.7~3.6V Speed(ns) Standby (ISB1, Max) 10A 10A 702)/85ns 20A 25mA 44-TSOP2-400F Operating (ICC2, Max) PKG Type
551)/702)/85ns
1. This parameter is measured with 30pF test load (Vcc=3.0~3.6V). 2. The parameter is measured with 30pF test load.
PIN DESCRIPTION
A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
Vcc Vss
44-TSOP2 Forward
Row Addresses
Row select
Memory array
I/O1~I/O8
Data cont Data cont Data cont
I/O Circuit Column select
I/O9~I/O16
Name CS OE WE A0~A17
Function Chip Select Input Output Enable Input Write Enable Input Address Inputs
Name Function Vcc Vss LB UB NC Power Ground Lower Byte (I/O1~8) Upper Byte (I/O9~16) No Connection
WE OE UB LB CS
Column Addresses
I/O1~I/O16 Data Input/Output
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2
Revision 1.0 August 2003
K6X4016T3F Family
PRODUCT LIST
Commercial Products(0~70C) Part Name
K6X4016T3F-TB551) K6X4016T3F-TB70 K6X4016T3F-TB85
CMOS SRAM
Industrial Products(-40~85C) Part Name
K6X4016T3F-TF551) K6X4016T3F-TF70 K6X4016T3F-TF85
Automotive Products(-40~125C) Part Name
K6X4016T3F-TQ70 K6X4016T3F-TQ85
Function
44-TSOP2-F, 55ns, LL 44-TSOP2-F, 70ns, LL 44-TSOP2-F, 85ns, LL
Function
44-TSOP2-F, 55ns, LL 44-TSOP2-F, 70ns, LL 44-TSOP2-F, 85ns, LL
Function
44-TSOP2-F, 70ns, L 44-TSOP2-F, 85ns, L
1. Operating voltage range is 3.0~3.6V
FUNCTIONAL DESCRIPTION
CS H L L L L L L L L OE X
1)
WE X
1)
LB X
1)
UB X
1)
I/O1~8 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din
I/O9~16 High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din
Mode Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Active Active Active Active Active Active Active Active
H X
1)
H X
1)
X1) H L H L L H L
X1) H H L L H L L
L L L X
1)
H H H L L L
X1) X1)
1. X means dont care. (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Symbol VIN,VOUT VCC PD TSTG Ratings -0.2 to VCC+0.3(max. 3.9V) -0.2 to 3.9 1.0 -65 to 150 0 to 70 Operating Temperature TA -40 to 85 -40 to 125 C Unit V V W C Remark K6X4016T3F-B K6X4016T3F-F K6X4016T3F-Q
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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K6X4016T3F Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage
Note: 1. Commercial Product: TA=0 to 70C, otherwise specified. Industrial Product: TA=-40 to 85C, otherwise specified. Automotive Product: TA=-40 to 125C, otherwise specified. 2. Overshoot: VCC+2.0V in case of pulse width 30ns. 3. Undershoot: -2.0V in case of pulse width 30ns. 4. Overshoot and undershoot are sampled, not 100% tested.
CMOS SRAM
Symbol Vcc Vss VIH VIL Min 2.7 0 2.2 -0.23) Typ 3.0/3.3 0 Max 3.6 0 Vcc+0.22) 0.6 Unit V V V V
CAPACITANCE1) (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ILI ILO ICC ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) VOL VOH ISB ISB1 VIL=Vss to Vcc CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc IIO=0mA, CS=VIL, VIN=VIL or VIH, Read Cycle time=1s, 100% duty, IIO=0mA CS0.2V, VIN0.2V or VINVcc-0.2V Cycle time=Min2), 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL IOL=2.1mA IOH=-1.0mA CS=VIH, Other inputs=VIL or VIH K6X4016T3F-B CSVcc-0.2V, Other inputs=0~Vcc K6X4016T3F-F K6X4016T3F-Q Test Conditions Min -1 -1 2.4 Typ Max 1 1 2 3 25 0.4 0.3 10 10 20 Unit A A mA mA mA V V mA A A A
-
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K6X4016T3F Family
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL
CMOS SRAM
CL1)
1.Including scope and jig capacitance
AC CHARACTERISTICS
( VCC=2.7~3.6V, Commercial product: TA=0 to 70C, Industrial product: TA=-40 to 85C, Automotive product: TA=-40 to 125C ) Speed Bins Parameter List Symbol 55ns1) Min Read cycle time Address access time Chip select to output Output enable to valid output LB, UB valid to data output Read Chip select to low-Z output Output enable to low-Z output LB, UB enable to low-Z output Output hold from address change Chip disable to high-Z output OE disable to high-Z output LB, UB disable to high-Z output Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write pulse width Write Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z LB, UB valid to end of write tRC tAA tCO tOE tBA tLZ tOLZ tBLZ tOH tHZ tOHZ tBHZ tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW tBW 55 10 5 5 10 0 0 0 55 45 0 45 40 0 0 25 0 5 45 Max 55 55 25 25 20 20 20 20 Min 70 10 5 5 10 0 0 0 70 60 0 60 55 0 0 30 0 5 60 70ns Max 70 70 35 35 25 25 25 25 Min 85 10 5 5 10 0 0 0 85 70 0 70 60 0 0 35 0 5 70 85ns Max 85 85 40 40 25 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
1. Voltage range is 3.0V~3.6V for commercial and industrial product.
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention Data retention current Symbol VDR IDR CSVcc-0.2V K6X4016T3F-B Vcc=3.0V, CSVcc-0.2V K6X4016T3F-F K6X4016T3F-Q Data retention set-up time Recovery time tSDR tRDR See data retention waveform 0 5 Test Condition Min 2.0 Typ Max 3.6 10 10 20 Unit V A A A ms
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K6X4016T3F Family
TIMING DIAGRAMS
CMOS SRAM
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC Address tOH Data Out Previous Data Valid tAA Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO tOH
CS
tHZ UB, LB tBA tBHZ OE tOLZ tBLZ tLZ Data Valid tOE tOHZ
Data out
High-Z
NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
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Revision 1.0 August 2003
K6X4016T3F Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC Address tCW(2) CS tAW tBW tWP(1) WE tAS(3) tDW Data in High-Z tWHZ Data out Data Undefined Data Valid tOW tDH tWR(4)
CMOS SRAM
UB, LB
High-Z
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC Address tAS(3) CS tAW tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4)
Data out
High-Z
High-Z
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K6X4016T3F Family
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC Address tCW(2) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4)
CMOS SRAM
Data out
NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
VCC 2.7V tSDR Data Retention Mode tRDR
2.2V VDR CSVCC - 0.2V CS GND
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Revision 1.0 August 2003
K6X4016T3F Family
PACKAGE DIMENSIONS
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
CMOS SRAM
Unit: millimeter(inch)
0~8 0.25 ( ) 0.010
#44
#23 0.45 ~0.75 0.018 ~ 0.030
11.760.20 0.4630.008
10.16 0.400
( 0.50 ) 0.020
#1
#22 1.000.10 0.0390.004 1.20 MAX. 0.047
0.15 0
0 + 0.1 5 - 0.0 .004 +0 02 .006 - 0.0
18.81 MAX. 0.741 18.410.10 0.7250.004
( 0.805 ) 0.032
0.35 0.10 0.0140.004
0.80 0.0315
0.05 MIN. 0.002
0.10 0.004 MAX
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Revision 1.0 August 2003

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